1. Field of the Invention
The present invention relates to a semiconductor device, a wafer, and a method of designing and manufacturing the semiconductor device, and more particularly to a semiconductor device including a multilayer interconnect structure of two or more layers, provided with a unique feature in the interconnect layout in the interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects, to a wafer for manufacturing such a semiconductor device, and to a method of designing and manufacturing the semiconductor device.
2. Description of the Related Art
A macro block in an ASIC (Application Specific Integrated Circuit) includes three functional units, namely an I/O (Input/Output) unit, a gate array unit and a PLL (Phase Locked Loop). The gate array unit includes a plurality of basic cells, each of which is constituted of a pair of a P-MOS transistor and an N-MOS transistor. Such basic cells are generally called primitive cells. The I/O unit is constituted of a peripheral I/O that transmits and receives standardized signals.
FIG. 11 is a schematic plan view showing a configuration of a popular ASIC device, including a layout of the macro block.
The device includes an I/O block 1101 disposed serving as an input/output interface, in a peripheral region. In inner regions of the device, primitive blocks 1102, 1103 are disposed, and the primitive block 1103 includes a SRAM 1104 serving as a memory. Most of the current devices are provided with the SRAM 1104 that includes two stages of a high-speed SRAM and a high-density SPAM.
In the primitive block, a multilayer interconnect structure including two or more layers is employed for interconnection of the primitive cells. The multilayer interconnection in the ASIC device will be described hereunder, referring to some drawings.
FIG. 12 is an enlarged plan view showing a region 1105 in the primitive block 1102 of the ASIC device shown in FIG. 11. FIG. 12 only depicts the primitive cell, a second metal interconnect layer (herein after, interconnect layer M2) and a third metal interconnect layer (herein after, interconnect layer M3), omitting the remaining interconnect layers.
The size of the primitive cell 1203 constituted of the P-MOS transistor 1201 and the N-MOS transistor 1202, called as a cell height 1204, is an important factor in each device. The cell height 1204 is a fundamental unit that should be optimally designed, as the cell height 1204 determines the driving capability of the transistors. The cell height 1204 is determined by multiplying the basic size of the transistor by an integer, or dividing an I/O macro width 1205, which is approx. 50 nm, by an integer.
The interconnect layer M2 includes a power supply line 1206 and a signal line 1207, and the interconnect layer M3 includes a power supply line 1208 and a signal line 1209. The interconnect lines in the primitive block mainly include a power supply line, a clock tree system timing interconnect, a signal transmitting interconnect, and a local interconnect serving for functional devices, which are the dominant factors that determine the efficiency of the layout.
FIG. 13 is an enlarged fragmentary view of the primitive cell 1203 shown in FIG. 12. FIG. 13 only depicts the primitive cell 1203, a first metal interconnect layer (herein after, interconnect layer M1) and the interconnect layer M2, omitting the remaining interconnect layers. In the primitive cell 1203, a VDD 1301 and a VSS 1302, which are the power supply line of the interconnect layer M2, are disposed across the P-MOS transistor 1201 and the N-MOS transistor 1202 respectively. To the power supply mesh of the interconnect layer M2, a first metal interconnect (herein after, M1 interconnect) 1303 is connected through a via 1304. The M1 interconnect includes finely divided power supply lines, and is generally called the local interconnect.
FIG. 14 is a schematic diagram showing a configuration of a dual-stage inverter including the primitive cell. FIG. 14 only depicts a diffusion layer 1403 including a P-MOS transistor 1401 and an N-MOS transistor 1402, a gate electrode 1404 and the M1 interconnect 1406, omitting the remaining interconnect layers.
The gate electrode 1404 serves as an interconnect, in addition to working as the gate electrode for the P-MOS transistor 1401 and the N-MOS transistor 1402. The diffusion layer 1403 receives a power from the VDD or VSS, via a local interconnect of the M1 interconnect 1406 and a contact 1405.
The foregoing is the outline of the multilayer interconnect structure in the ASIC device, shown in FIGS. 12 to 14. The following passages cover a method of manufacturing the ASIC device including the tri-level interconnect layers constructed as above.
FIGS. 15A to 15F are schematic cross-sectional views for explaining a manufacturing method of the ASIC device including tri-level interconnect layers.
Referring first to FIG. 15A, an N-type source region 1502 and an N-type source drain region 1503, a gate insulating layer 1504 and a gate electrode 1505 are formed on a P-type silicon substrate 1501 by a known photolithography and ion implantation process, and a CVD (Chemical Vapor Deposition) process is performed to form a first inter layer dielectric 1506 constituted of a silicon oxide layer, all over the substrate. A plurality of MOS transistors thus formed is routed through the subsequent steps.
Referring to FIG. 15B, a via is formed in the first inter layer dielectric 1506 by photolithography, after which the via is filled with tungsten (W) to thus form a plug conductor 1507.
Proceeding to FIG. 15C, an insulating layer 1508 constituted of a silicon oxide layer by CVD, and then an interconnect trench 1509 is formed in a predetermined pattern by photolithography, at a desired position on the insulating layer 1508.
Referring then to FIG. 15D, a conductor layer 1510 constituted of copper (Cu) or aluminum (Al) is formed by CVD all over the insulating layer 1508 including the interconnect trench 1509.
At FIG. 15E, a CMP (Chemical Mechanical Polishing) process is performed for planarizing the surface of the second inter layer dielectric 1508. Upon completing the CMP process, the M1 interconnect of a Damascene structure is obtained in a strap shape at the desired position on the second inter layer dielectric 1508.
The above is followed by repetitions of similar steps to those corresponding to FIGS. 15A to 15E, to achieve a structure shown in FIG. 15F. Specifically, a second inter layer dielectric 1512, an interconnect layer M2 1513, a third inter layer dielectric 1514, an interconnect layer M3 1515, and a fourth inter layer dielectric 1516 are formed on the interconnect layer M1 1511. The fourth inter layer dielectric 1516 serves to protect the MOS transistor from the ambient atmosphere. Finally an electrode 1517 is formed, to thereby complete the fabrication of the semiconductor device including the tri-level interconnect layers.
The following passages describe the photolithography process employed in the foregoing method of manufacturing.
The exposure technique for semiconductor devices has been innovated along with the micronization of the devices, as stated in the non-patented documents 1 and 2. The exposure method has also been shifted from a “step & repeat” method of repeating reduction projection of a reticle on different positions on a wafer, to a scanning method of causing the reticle and the wafer to relatively move for the exposure. This is because the stepper type exposure equipments are no longer capable of satisfying severe requirements originating from the ongoing micronization of the circuit pattern of the devices. Instead, the development of the scanning type exposure equipments has enabled satisfying required precision in dimensions and overlay when exposing a pattern of 100 nm or less in size, in addition to a shorter wavelength of a light source and higher numerical apertures.
FIG. 16 is a schematic side view showing a popular scanning type exposure equipment.
An ArF (argon fluoride) beam of 1.725 nm in wavelength irradiated by a light source 1601 is projected on a wafer 1603 through a reticle 1602. The pattern delineated on the reticle is reduced to a quarter in dimensions by two lens systems 1604, 1605. A reticle scanning stage 1606 and a wafer scanning stage 1607 are synchronically scanned, and a relative positional deviation is controlled. In the stepper-type exposure equipment the stage is immobile during the exposure since the entire pattern is exposed by turns. In contrast, in the scanning type exposure equipment the pattern is exposed real time, while the stage is being moved for scanning.
FIGS. 17A and 17B are schematic plan views showing a positional relation between a lens and an exposure region, in the stepper-type exposure equipment and the scanning type exposure equipment.
As shown in FIG. 17A, the exposure region 1702 is enclosed in the lens 1701, so that a major portion of the lens 1701 is utilized for the exposure, in the stepping equipment. In contrast, in the scanning equipment shown in FIG. 17B, a slot 1704 is provided at an appropriate position of the lens 1703, so as to utilize such portion for scanning to cover the exposure region 1705. This method allows utilizing only a portion of the lens where aberration is minimal for the exposure, thus providing an excellent exposure characteristic.
[Non-patented document 1] Tatsuhiko HIGASHIKI, “Photolithography: Practical Fundamentals and Challenges”, ED Research Co., Ltd., Jul. 1, 2002
[Non-patented document 2] Tatsuhiko HIGASHIKI, “Photolithography II: Measurement and Control”, ED Research Co., Ltd., Jun. 10, 2003
As described above, the scanning type exposure equipment is now indispensable for satisfying a fine interconnect spec, because of its higher exposure characteristic.
However, the scanning type exposure equipment is not free from drawbacks, such as being susceptible to vibration during the movement for the scanning, since the exposure is performed parallel to the scanning. A precision under such a state is referred to as “synchronization accuracy”. The synchronization accuracy is determined by an average (MEAN) value of a relative travel distance of the slot on the reticle with respect to the wafer, and a MSD (Moving Standard Deviation) of the travel distance.
FIG. 18 is a schematic diagram showing a positional deviation created by the relative movement of the reticle.
For the purpose of the description, the slot 1801 on the reticle is assumed to move to a position 1802 during the scanning. The position where the slot actually reaches may be deviated as a position 1803 or a position 1804, because of vibration or other reasons. The travel distances in such cases (1805, 1806) include a deviation 1808, 1809 respectively, with respect to the average distance 1807. The fluctuation of the deviation is represented by the MSD of the travel distance. The more the average of the travel distance deviates from the standard value, the lower the pattern overlay accuracy becomes, and when the MSD of the travel distance becomes greater, the contrast in the image becomes lower. Such problem with the synchronization accuracy originating from vibration is unique to the scanning type exposure equipment, not observed with respect to the stepping type exposure equipment.
For improving the synchronization accuracy, restraining the vibration is one of the measures to be taken. The vibration includes not only an external vibration generated by a factor outside the equipment, but also a vibration generated by the scanning motion as already mentioned. For restraining the vibration generated by the scanning motion, heavy restriction should be imposed on the specifications of the equipment, since the issue relates to manufacturing interconnects of a scale level of 100 nm. In short, the expected throughput of the equipment and the synchronization accuracy are trade-off factors.
Also, a microlithography for forming interconnects in a scale level of 100 nm incurs a phenomenon that a dimensional fluctuation of the mask pattern on the reticle becomes non-linear with respect to an exposure pattern fluctuation. This is called a MEEF (Mask Error Enhancement Factor) between the mask dimensional fluctuation and the wafer dimensional fluctuation. As shown in FIG. 17B, the exposure light only passes a portion of the lens, in the scanning equipment. This leads to a partially coherent exposure, so that in the limit of resolution the contrast in the pattern image formed on the wafer is degraded. Between the MEEF and the mask pattern, a general tendency can be seen that a progress in micronization leads to an increase in MEEF, which in turn increases the dimensional fluctuation of the resist pattern.
In the scanning type exposure equipment of a reduction ratio of ¼, the pattern on the reticle is reduced to ¼ in dimensions when transferred onto the wafer. When the MEEF is 1, the dimensional fluctuation of 10 nm on the reticle is reduced to 2.5 nm on the wafer. On the other hand, when the MEEF is 5, the fluctuation is enlarged to as much as 12.5 nm.
As described above, the error resultant from focus fluctuation based on the MEEF imposes a significant difficulty in establishing a size budget in the microlithography of a scale level of 100 nm. This makes the issue of the synchronization accuracy more complicated, thereby enhancing the importance of upgrading the synchronization accuracy.